1. Technical Field
The present application relates generally to an improved integrated circuit apparatus and method. More specifically, the present application is directed to a level shifter apparatus and method for minimizing duty cycle distortion.
2. Description of Related Art
Level shifters are integral components of any circuit that operates from different power supply boundaries. The level shifters act as the interfaces between these different power supply domains to send/receive signals across these boundaries. However, the voltage mismatch between the two power domains may cause severe duty cycle errors if simple receivers are used for level shifting. This error gets worse as the mismatch in the power supply voltages between the two domains gets larger. To appreciate this, a simple explanation of how a simple level shifter works is provided below.
FIG. 1 illustrates a simple level shifter in accordance with a known implementation. The level shifter shown in FIG. 1 operates as an inverter. The voltage input VIN to the level shifter 100 comes from a first power domain 110, having voltage source VDDC and ground GNDC, and circuits 115 operating based on voltage source VDDC and ground GNDC. The level shifter 100 itself resides in a second power domain 120, having voltage source VDDA and ground GNDA. It is assumed, for this explanation that GNDC=GNDA=gnd. The main failure mechanism in such a level shifter 100 as shown in FIG. 1 is the mismatch in the drive strength between the pull-up PFET 130 and the pull down NFET 140.
Suppose that initially the output of the level shifter 100 is high (VDDA). The capacitance loading the output node of the level shifter, CL, is the loading due to the circuitry 125 being driven by the level shifter 100. It is assumed that the threshold voltage at which the circuitry 125 changes its state is called V_TRIP.
At time t0, the voltage input, VIN, to the level shifter 100 changes from low to high (gnd to VDDC). At this instant, the maximum pull down current provided by the NFET 140 may be described as:INMAX=KN*(VDDC−VTN)α  (1)
where KN is a transconductance parameter taking into account device size, mobility, etc., VTN is the NFET 140 threshold voltage, and α is a fitting parameter that may vary with process (e.g., doping, threshold voltage, mobility, gate oxide thickness etc. variations across a single wafer and across multiple wafers), as well as device length.
At t0, the maximum discharge current from CL is given by:ICLmax=CL*(δVout/δt)max  (2)
where Vout is the output voltage of the level shifter. Assuming VDDA>VDDC, then the pull-up current still provided by the PFET 130 can be modeled as:IP=f(VDDA−VDDC)  (3)
where f( ) is a monotonically increasing function of VDDA−VDDC. Hence, the larger VDDA-VDDC, the larger the pull-up current will be. Applying Kirkoff's current law to t0, one may write:CL(δVout/δt)MAX=INMAX−f(VDDA−VDDC)  (4)(δVout/δt)MAX=[INMAX−f(VDDA−VDDC)]/CL  (5)
FIG. 2 displays Vout versus time plots for various VDDA−VDDC settings. That is, FIG. 2 describes the time transient of Vout upon the instantaneous switch in state of the input VIN (from 0 to VDDC). The various traces for Vout correspond to various VDDA−VDDC values. The value of V_TRIP is also shown in FIG. 2.
It can be seen from FIG. 2 that for larger VDDA−VDDC settings, the δVout/δt gradient is reduced causing the amount of time it takes for Vout to reach V_TRIP to be increased. This time, labeled T_TRIP, can be used to directly compute the maximum frequency of operation of the level shifter for a given VDDA−VDDC setting:FMAX<1/(2*T_TRIP)  (6)Thus, the increase in the T_TRIP value also reduces the maximum operating frequency of the level shifter.
In addition, T_TRIP can provide information about the duty cycle distortion introduced by this circuit. In the worst case where INMAX=f(VDDA−VDDC), Vout will never discharge and the level shifter has become useless.
There are many level shifter circuits presently available, e.g., U.S. Pat. No. 6,940,333 describes as high-to-low level shifter in which an external signal switches between a high voltage domain high potential and a high voltage domain low potential while an internal signal switches between a low voltage domain high potential and a low voltage domain low potential. However, these known level shifter circuits do not address the issues arising due to high frequency operation.